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Ali Akoglu is an Professor in the Department of Electrical and Computer Engineering and the BIO5 Institute at the University of Arizona. He is the site-director of the National Science Foundation (NSF), Industry-University Cooperative Research Center on Cloud and Autonomic Computing regarding the design and development of architectures for achieving self-management capabilities across the layers of cloud computing systems, director of the NVIDIA CUDA Teaching Center for promoting the GPU based computing across the UA campus, and the director of the Reconfigurable Computing Laboratory on design and development of adaptive hardware architectures and self-configurable architectures for reusable systems. He received his Ph.D. degree in Computer Science from the Arizona State University in 2005. His research program focuses on high performance computing systems and non-traditional computing architectures with themes that cover: a) development of resource management strategies from multi-processor system-on-chip to cloud computing scale; b) design and development of reconfigurable hardware architectures for reusable systems; c) modeling and simulation of neuromorphic computing architectures; and d) restructuring computationally challenging algorithms for achieving high performance on field programmable gate array (FPGA) and graphics processing unit (GPU) hardware architectures. He has been involved in many crosscutting collaborative projects with the goal of solving the challenges of bridging the gap between the domain scientist, programming environment and emerging highly-parallel hardware architectures. His research projects have been funded by the National Science Foundation, Defense Advanced Research Projects Agency, Office of Naval Research, US Air Force, NASA Jet Propulsion Laboratories, Army Battle Command Battle Laboratory, and industry partners such as Nvidia and Raytheon.Show Less
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Courses
- RCReconfigurable Computing
- HPCTAAHigh Performance Computing: Technology, Architecture, and Algorithms
- CADComputer Architecture and Design
- DLDigital Logic
- FCAFundamentals of Computer Architecture
- FCOFundamentals of Computer Organization
Grants
- CCRI: Planning-C: Federated Cloud Platform for Networked Cyber Physical Systems Research
Co-Investigator (COI)
2022
$100.0K
Active - Domain-Focused Advanced Software-Reconfigurable Heterogeneous System on Chip (DASH-SoC)
Principal Investigator (PI)
2022
$50.0K
Active - IUCRC: CAC: Non-Fungible Token (NFT) based Digital Rights Management (NFT-DRM)
Co-Investigator (COI)
2022
$47.7K
Active - Artificial Intelligence (AI) based Reputation Management Service (AI-RMS)
Co-Investigator (COI)
2022
$23.9K
Active - Dynamic Spectrum Sharing 5G Applications Prototype Contract
Co-Investigator (COI)
2021
$1.0M
Active - Space-Based Adaptive Communications Node (Space-BACN) Program.
Principal Investigator (PI)
2021
$319.1K
Active - Phase-II IUCRC Texas Tech University: Center for Cloud and Autonomic Computing
Co-Investigator (COI)
2021
$95.5K
Active - Phase-II IUCRC Texas Tech University: Center for Cloud and Autonomic Computing
Co-Investigator (COI)
2021
$26.7K
Active - SBIR Phase II: High Performance Machine Learning Framework (HPMLF)
Principal Investigator (PI)
2019
$200.0K
Active - Domain-Focused Advanced Software-Reconfigurable Heterogeneous System on Chip DAS-SoC
Principal Investigator (PI)
2018
$1.4M
Active
Technologies / Patents
News
- Grand Challenge: Mapping the Human Immune System
2016
- UA Researchers Create Self-Healing Computer Systems for Spacecraft
2008
- Students Design User-Friendly Kitchen Range for Elderly, Disabled
2007
Publications (57)
Recent
- CEDR - A Compiler-integrated, Extensible DSSoC
2021
- Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous SoCs
2021
- FPGA Based High-Throughput Real-Time Feature Extraction for Modulation Classification
2020
- GPGPU Based Parallel Implementation of Spectral Correlation Density Function
2020
- DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework
2020
- Reduction of Effective Pixel Pitch of Digital Micromirror Device for Lidar Transmitter and Receiver
2020
- Implementation of IBM's TrueNorth Chip on a Field Programmable Gate Array
2020
- RANC: Reconfigurable Architecture for Neuromorphic Computing
2020
- User-Space Emulation Framework for Domain-Specific SoC Design
2020
- A Value-Oriented Job Scheduling Approach for Power-Constrained and Oversubscribed HPC Systems
2020
- Dynamic power management for value-oriented schedulers in power-constrained HPC system
2020
- FPGA Based Emulation Environment for Neuromorphic Architectures
2020
- Adaptive Power Reallocation for Value-Oriented Schedulers in Power-Constrained HPC
2019
- Utility-based resource management in an oversubscribed energy-constrained heterogeneous environment executing parallel applications
2019
- Implementation of scalable bidomain-based 3d cardiac simulations on a graphics processing unit cluster
2019
- A simulation framework for domain-specific system-on-chips: work-in-progress
2019
- Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes
2019
- Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips
2019
- Bit-wise and Multi-GPU Implementations of the DNA Recombination Algorithm
2019
- Accelerated Shadow Detection and Removal Method
2019
- Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures
2018
- Real-Time GPU Based Video Segmentation with Depth Information
2018
- Balancing the learning ability and memory demand of a perceptron-based dynamically trainable neural network
2018
- Gpu based quarter spectral correlation density function
2018
- Hardware implementation and performance analysis of resource efficient probabilistic hard decision LDPC decoders
2018
- Two-Level Autonomous Optimizations Based on ML for Cardiac FEM Simulations
2018
- Post-Routing Analytical Wirelength Model for Homogeneous FPGA
2017
- Multi-mode Low-latency Software-defined Error Correction for Data Centers (Invited Paper)
2017
- Analysis and Implementation of Resource Efficient Probabilistic LDPC Decoder: Trade-offs Between the Decoding Performance and Hardware Performance
2017
- Value-Based Scheduling for Oversubscribed Power-Constrained Homogeneous HPC Systems
2017
- Integrated Optical Network-On-Chips for Dynamically Composable Data Center
2017
- High Performance Machine Learning (HPML) Framework to Support DDDAS Decision Support Systems: Design Overview
2017
- Design of a Perceptron Based Dynamically Trainable Neural Network: Balancing the Learning Ability and Hardware Resource Demand with a Case Study on the Perceptron-Based Branch Predictor
2017
- Application-Specific Autonomic Cache Tuning for General Purpose GPUs
2017
- Efficient FPGA Implementation of Probabilistic Gallager B LDPC Decoder
2017
- Value of Service Based Resource Management for Large-Scale Computing Systems
2017
- Autonomic Management of 3D Cardiac Simulations (Best Paper Award)
2017
- Just In Time Architecture (JITA) for Dynamically Composable Data Centers
2016
- iWAS-A novel approach to analyzing Next Generation Sequence data for immunology
2016
- Resource Efficient Real-Time Processing of Contrast Limited Adaptive Histogram Equalization
2016
- Value of Service Based Task Scheduling for Cloud Computing Systems
2016
- Value-Based Resource Management in High-Performance Computing Systems
2016
- An Autonomic Workflow Performance Manager for Weather Research and Forecast Workflows
2016
- GPU and FPGA Based Architecture Design for Real-time Signal Classification
2015
- Overcoming the Limitations Posed by TCR-beta Repertoire Modeling through a GPU-Based In-Silico DNA Recombination Algorithm
2014
- Autonomic Workload and Resources Management of Cloud Computing Resources
2014
- A Power Efficient Reconfigurable System-in-Stack: 3D integration of accelerators, FPGAs, and DRAM
2014
- An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
2013
- Integration of Net-Length Factor with Timing-and Routability-Driven Clustering Algorithms
2013
- A Hybrid FPGA Model to Estimate On-Chip Crossbar Logic Utilization in SoC Platforms
2013
- FPGA based single cycle, reconfigurable router for NoC applications
2013
- An adaptive motion estimation architecture for H. 264/AVC
2013
- WL-Emap: Wirelength prediction based technology mapping for FPGAs
2012
- Quantitative Trait Locus Analysis Using a Partitioned Linear Model on a GPU Cluster
2012
- Cardiac simulation on multi-GPU platform
2012
- Bit-by-bit pipelined and hybrid-grained 2d architecture for motion estimation of h. 264/avc
2012
- High performance biological pairwise sequence alignment: FPGA versus GPU versus cell BE versus GPP
2012